I am having trouble learning how to model n bit wide mux's in verilog.
I am trying to gate level model a 2 bit wide multiplexer, here is my current code:
Verilog modules, ports and wires. Gate-level circuit models, quickly become very unwieldy to manage. In Verilog, we can manage this complexity by grouping logic gates together into modules.A module is a subset of the circuit which can be used as a building block in the design of the entire circuit. Blocks usually carry out specific functions. Verilog Code for 2:1 MUX using if statements This post is for Verilog beginners. 2:1 MUX is a very simple digital block with 2 data inputs, one select input and one data output. The code follows Behavioral modelling. There are many ways you can write a code for 2:1 mux. Verilog code for 2:1 MUX using Gate level modellin.
I am receiving the following error messages:
Can anyone help me out or point me in the right direction for some easy understanding of how to implement this?
TomTom
2 Answers
Multi-bit buses are declared like this
![Mux Gate Level Verilog Mux Gate Level Verilog](http://www.altera.co.kr/_hdl/2/RESOURCES/www.ee.ed.ac.uk/~gerard/Teach/Verilog/me5cds/mux21_sw.gif)
and not like this
mkrieger1mkrieger1
Besides the bus declaration issue described by mkrieger1 you have several other issues that you need to take care of.
Currently you have multiple drivers on t0 and t1. It appears from the logic that you want t0 and t1 to be 2 bit buses as well, but you are using an implicit declaration of those signals which will create single bit signals. For example that means that these two instances are both driving the same signal:
In this case you will get an X value whenever these gates differ in their output.
If instead you declared these signals and make them 2 bits, then the following would work as you want:
Then you have the issue of doing multiple bit implementations using a gate, specifically the OR gate. A simple gate only works with one bit outputs, but they can work on an array. That is done by declaring an array of instances. You haven't used instance names, but to accomplish this you will need an instance name and a range declaration. The following would work for your OR gate:
That will perform the operation on both bits of those 3 signals.
Overall the most compact implementation would be something like:
In this case I've also used the array form for the AND gates. In this case note that they are 2 bits wide, but the s and sbar inputs are just one bit wide. Verilog handles that by using those one bit signals for all the bits of the gate.
Brad BudlongBrad Budlong
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I have the following initiation in gate level Verilog.
In my poor understanding 'Z' pin of buffer is connected to : 'mux_inst/aggr_portd_inst/dskw_inst/ds_mem_slice_4__5_3'
1.But the connection of 'A' is not clear.
2.Should be there space between [4] and [5] or not?
2.Should be there space between [4] and [5] or not?
user3597530user3597530
2 Answers
![Verilog Verilog](/uploads/1/2/5/0/125015867/504859506.png)
Synthesis tools can perform two operations on your design:
-
Flattening: They convert your hierarchical design into a single module in which there is no hierarchy. In this case, all signal names in the flatten module corresponding to signals in the non-flatten module
mux_inst.aggr_portd_inst.dskw_inst
will have the prefix name:mux_inst/aggr_portd_inst/dskw_inst
. The ' is used to escape '/' character. -
Bit-blasting: Bit-blasting is the term for breaking down a bus/array into its individual members. For example, an array which was originally defined as
logic [2:0] array
will be broken into:
Again, the ' is used to escape '[' and ']' characters. If they array was two-dimensional, you would have:
logic array[2][0] ;
, which acts like a single wire corresponding to member [2][0] of the array.
In your case, it looks like the synthesizer performed both flattening and bit-blasting.
There might be a rare occasion, where the synthesizer performs bit-blasting on only one dimension and keep the other dimension as an array. In that case,
array[2] [0] ;
has a different meaning than logic array[2][0] ;
. The former is the member 0 of an array called array[2]
, whereas the latter is a single wire which was the result of bit-blasting, corresponding to the index [2][0] of the array before bit-blasting.
AriAri
With Verilog binary words each bit can be accessed with an array like syntax.
Extra dimensions can be add, the most basic 2 dimensional array often being called a memory. Here with syntax used previously the first
[]
access a word, using double [][]
we access a single bit.
Therefore if
ds_mem_slice
is declared as a memory then mux_inst/aggr_portd_inst/dskw_inst/ds_mem_slice[4][5]
is accessing a single bit of it. Word 4 bit 5.
MorganMorgan